Micro-nano lithography

• Our aim : To understand the lithographic behaviour of materials at the nanoscale. To find the material / process origins of Line Edge/Width Roughness (LER or LWR) and propose solutions for its reduction.

This can be achieved by means of:
1. Stochastic simulation of lithographic process
2. Modeling of LER / LWR impact on transistor performance
3. Metrology and characterization of LER / LWR

1. Stochastic Simulation of lithography for LER reduction

We have developed a 2D and 3D lithography simulator, which inputs individual photoresist molecules / chains, photoacid generator molecules and performs all lithography steps (exposure, PEB, reaction-diffusion, development).

2. Modeling of LER impact on transistor performance

“Slicing” the gate in order to take into accound LWR we can then apply SPICE like electrical analysis and determine quantities such as threshold voltage shift or leakage current variations in terms of LWR.

3. Metrology and characterization of LER/LWR

Metrology : LER/LWR extraction from top-down SEM images.

Characterization : a three parameter model.

a) σ_LWR(inf): the sigma value of the infinite line length.
A line length independent LWR metric:
3σ_LWR² (inf) =3σ_LWR² (L) +3CDvariation²(L)

b) Correlation length ξ : The line length after which line widths are
almost uncorrelated and for L_S>~10ξ σ_LWR(L>L_S) saturates to σ_LWR(inf)

c) Roughness exponent a:
It gives the relative contribution of high frequency roughness to LWR.
It is related to fractal dimension d=2-α

A demo of our software is available on our web page, see under software.